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COMMUNICATION SEMICONDUCTORS
MX641
Dual SPM Detector
PRELIMINARY INFORMATION
DATA BULLETIN
Features
* Two (12kHz / 16kHz) SPM Detectors on a Single Chip * Detects 12 or 16kHz SPM Frequencies * `Controlled' (C) & `Fixed' Signal Sensitivity Modes * Selectable Tone Follower or Packet Mode Outputs * High Speech-Band Rejection Properties * `Output Enable' Multiplexing Facility
CLOCK OUT XTAL/CLOCK XTAL/CLOCK GENERATOR XTAL BUFFER
Applications
* Call Charge Applications on PABX Line Cards * Remote Telephone Applications
CLOCK IN CLOCK DIVIDERS
INTERNAL CLOCKS
VDD VBIAS VSS
12kHz/16kHz SYSTEM
Ch 1 AMP OUT Ch1 AMP IN (-)
Ch 1 COMPARATOR
TONE FOLLOWER MODE
Ch 1 OUTPUT OUTPUT SELECT CIRCUITS
Ch1 AMP IN (+)
Ch 1 INPUT AMPLIFIER
GAIN ADJUST
INTERNAL COMPARATOR THRESHOLD
PRESET LEVEL CHIP SELECT SERIAL DATA
12kHz/16kHz SYSTEM
SERIAL INPUT LOGIC
LEVEL/ SYSTEM SETTING
SERIAL CLOCK SYSTEM SELECT
Ch 2 INPUT AMPLIFIER GAIN ADJUST INTERNAL COMPARATOR THRESHOLD
Ch2 AMP IN (-)
Ch 2 BANDPASS FILTER
Ch2 AMP IN (+) Ch 2 AMP OUT
Ch 2 COMPARATOR TONE FOLLOWER MODE
The MX641 is a low-power, system-selectable Dual Subscriber Pulse Metering (SPM) Detector designed to indicate the presence, on a telephone line, of either 12kHz or 16kHz telephone call-charge frequencies. It is designed for PBX and PABX line-card and remote telephone installations. Under Processor control via a common serial interface, each channel of the MX641 will detect call-charge pulses from a telephone line and provide a digital output for recording, billing or security purposes. A common set of external components and a stable 3.579545MHz Xtal/clock input ensures that the MX641 adheres accurately to most national "Must and Must-Not" decode band-edges and threshold levels. For non-Processor systems a preset sensitivity/system input allows external channel level and system setting The digital output is pin-selectable to one of three modes: (1) Tone Follower mode: logic level for the period of a correct decode. (2) Packet mode: respond/de-respond after a cumulative period of tone or notone in a fixed (intrinsic hardwired period that is not user controlled) period. (3) High-impedance output: for device multiplexing. The MX641 requires a 5V supply and is available in the following packages: 24-pin SOIC (MX641DW) and 24-pin PDIP (MX641P)
a2001 MX-COM, Inc.
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+ + -
Ch 1 BANDPASS FILTER
PULSE GENERATOR AND DIVIDER
-
+ + -
-
PULSE MEASUREMENT LOGIC
PULSE LENGTH LOGIC
PACKET MODE
CHANNEL 1
OUTPUT ENABLE
12kHz/16kHz SYSTEM
OUTPUT SELECT
CHANNEL 2
PULSE GENERATOR AND DIVIDER
PACKET MODE
PULSE MEASUREMENT LOGIC
PULSE LENGTH LOGIC
OUTPUT SELECT CIRCUITS Ch 2 OUTPUT
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Dual SPM Detector
Page 2 of 16
MX641 Preliminary Information
CONTENTS
Section Page
1. Block Diagram ............................................................................................................... 3 2. Signal List ...................................................................................................................... 4 3. External Components ................................................................................................... 6 4. General Description ...................................................................................................... 7
4.1 4.2 4.3 Xtal/Clock Distribution........................................................................................................ 7 Channel Outputs................................................................................................................ 7 Sensitivity Setting .............................................................................................................. 8
4.3.1 4.3.2 Controlled Sensitivity Setting .................................................................................................. 8 Fixed Sensitivity Setting........................................................................................................ 11
5. Applications................................................................................................................. 12
5.1.1 5.1.2 5.1.3 Input Configurations.............................................................................................................. 12 Protection Against High Voltages ......................................................................................... 12 Aliasing ................................................................................................................................. 12
6. Performance Specification ......................................................................................... 13
6.1 Electrical Specifications ................................................................................................... 13
6.1.1 6.1.2 6.1.3 Absolute Maximum Ratings .................................................................................................. 13 Operating Limits.................................................................................................................... 13 Operating Characteristics ..................................................................................................... 13
6.2 6.3
Timing.............................................................................................................................. 15 Packages......................................................................................................................... 16
MX*COM, Inc. reserves the right to change specifications at any time and without notice.
a2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480115.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Dual SPM Detector
Ch 1 BANDPASS FILTER
PULSE MEASUREMENT LOGIC
Ch1 AMP IN (+)
Ch 1 INPUT AMPLIFIER GAIN ADJUST INTERNAL COMPARATOR THRESHOLD
Ch2 AMP IN (+)
Ch 2 COMPARATOR TONE FOLLOWER MODE
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12kHz/16kHz SYSTEM
MX641 Preliminary Information
Doc. # 20480115.004
Ch 2 AMP OUT
+
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12kHz/16kHz SYSTEM Ch 1 COMPARATOR
-
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CLOCK OUT XTAL/CLOCK GENERATOR BUFFER CLOCK DIVIDERS
INTERNAL CLOCKS
PRESET LEVEL
Page 3 of 16
CHIP SELECT SERIAL INPUT LOGIC LEVEL/ SYSTEM SETTING
12kHz/16kHz SYSTEM
Figure 1: Block Diagram
SERIAL DATA
SERIAL CLOCK
INTERNAL COMPARATOR THRESHOLD
SYSTEM SELECT
Ch 2 INPUT AMPLIFIER GAIN ADJUST
Ch2 AMP IN (-) Ch 2 BANDPASS FILTER
+
+ -
-
+
-
a2001 MX-COM, Inc.
CLOCK IN VDD VBIAS VSS
TONE FOLLOWER MODE
XTAL/CLOCK
1. Block Diagram
XTAL
Ch 1 AMP OUT
Ch 1 OUTPUT PULSE LENGTH LOGIC
PACKET MODE
Ch1 AMP IN (-)
PULSE GENERATOR AND DIVIDER
OUTPUT SELECT CIRCUITS
CHANNEL 1
OUTPUT ENABLE
OUTPUT SELECT
CHANNEL 2
PULSE GENERATOR AND DIVIDER
PACKET MODE
PULSE MEASUREMENT LOGIC
PULSE LENGTH LOGIC
OUTPUT SELECT CIRCUITS Ch 2 OUTPUT
Dual SPM Detector
Page 4 of 16
MX641 Preliminary Information
2. Signal List
Pin No. 1 Name Xtal/Clock Type input Description The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in conjunction with the Xtal output; circuit components are on-chip. When using a Xtal input, the Clock Out pin should be connected directly to the Clock In pin. If a clock pulse input is used at the Clock In pin, this (Xtal/Clock) pin must be connected directly to VDD (see Figure 2). See Figure 3 for details of clock frequency distribution. The output of the on-chip clock oscillator inverter. The buffered output of the on-chip-clock oscillator inverter. If a Xtal input is used, this output should be connected directly to the Clock In pin. This output can support up to 3 additional MX641 ICs. See Figure 3 for details of clock frequency distribution. The 3.579545 clock pulse input to the internal clock dividers. If an externally generated clock pulse input is used, the Xtal/Clock input pin should be connected to VDD.
2 3
XTAL
output output
Clock Out
4
Clock In
input
5
Output Enable
input
For multi-chip output multiplexing; controls the state of both Ch1 and Ch2 outputs. When this input is placed high (logic '1') both outputs are set to a high impedance. When placed low (logic '0') both outputs are enabled. The digital output of the Channel 2 SPM detector when enabled. The format of the signal at this pin, in common with Ch 1, is selectable to either 'Tone Follower' or 'Packet' mode via the Output Select input. The digital output of the Channel 1 SPM detector when enabled. The format of the signal at this pin, in common with Ch 2, is selectable to either 'Tone Follower' or 'Packet' mode via the Output Select input. The output of the on-chip analog bias circuitry. Held internally at VDD/2, this pin should be decoupled to VSS (see Figure 2). The output of the Channel 1 Input Amplifier. See Figure 2 and Figure 8. The negative input to the Channel 1 Input Amplifier. See Figure 2 and Figure 8. The positive input to the Channel 1 Input Amplifier. See Figure 2 and Figure 8. Negative supply (GND). No internal connection; leave open circuit. The positive input to the Channel 2 Input Amplifier. See Figure 2 and Figure 8. The negative input to the Channel 2 Input Amplifier. See Figure 2 and Figure 8. The output of the Channel 2 Input Amplifier. See Figure 2 and Figure 8. A logic input to set the Channel 1 and Channel 2 output modes. When high (logic '1'), the outputs are in the Tone Follower mode; when low (logic '0'), the outputs are in the Packet mode. A logic input to set the sensitivity mode of the MX641. When high (logic '1'), both channels are in the Fixed Sensitivity mode. The external components govern the input sensitivity; the System Select input selects 12kHz or 16kHz operation. When low (logic '0'), both channels are in the Controlled Sensitivity mode. Device sensitivities and system selection are via the Chip Select/Serial Data/Serial Clock inputs. This input has an internal pull-up resistor on chip (Fixed Sensitivity Mode).
6
Ch 2 Output
output
7
Ch 1 Output
output
8 9 10 11 12 13 14 15 16 17
VBIAS Ch 1 Amp Out Ch 1 Amp In (-): Ch 1 Amp In (+): VSS N/C Ch 2 Amp In (+): Ch 2 Amp In (-): Ch 2 Amp Out Output Select
power output input input power input input output input
18
Preset Level
input
a2001 MX-COM, Inc.
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Dual SPM Detector
Page 5 of 16
MX641 Preliminary Information
Pin No.
Name
Type
Description
19
Chip Select
input
The Chip Select input for use in data loading when using the MX641 in the Controlled Sensitivity mode (see Figure 9). The device is selected when this input is set low (logic '0'). When the MX641 is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD. The Serial Clock input for use in data loading when using the MX641 in the Controlled Sensitivity mode (see Figure 9). Data is loaded to the MX641 on this clock's rising edge. When the MX641 is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD. The Serial Data input for use in data loading when using the MX641 in the Controlled Sensitivity mode (see Figure 9 and Table 4). When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD. In the Fixed Sensitivity mode this pin selects the system frequency. High (logic `1') = 12kHz; Low (logic `0') = 16kHz. In the Controlled Sensitivity mode this pin should be tied to VDD or left unconnected. This pin has an internal pull-up resistor on chip. No internal connection; leave open circuit. Positive supply rail; a single, stable power supply is required. Critical levels and voltages within the MX641 are dependent upon this supply. This pin should be decoupled to VSS by a capacitor mounted close to the pin
Table 1: Signal List
20
Serial Clock
input
21
Serial Data
input
22
System Select
input
23 24
N/C VDD power
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Dual SPM Detector
Page 6 of 16
MX641 Preliminary Information
3. External Components
VDD XTAL/CLOCK
If you use a Clock Pulse input: - Remove Xtal (X1) - Connect Pin 1 to VDD - Do not short Pins 3 & 4 - Input clock pulses to CLOCK IN See Figure 3
VDD XTAL/CLOCK
X1
CLOCK IN
XTAL OUT CLOCK IN OUTPUT ENABLE CH2 OUTPUT CH1 OUTPUT VBIAS CH1 AMP OUT
C3 C4
CH1 AMP IN (-)
R2 R1
R3
CH1 AMP IN (+)
R4 R8 C2
VSS
1 2 3 4 5 6 7 8 9 10 11 12
MX641
24 23 22 21 20 19 18 17 16 15 14 13
VDD
C1
SYSTEM SELECT SERIAL DATA SERIAL CLOCK CHIP SELECT PRESET LEVEL OUTPUT SELECT CH2 AMP OUT
R7
CH2 AMP IN (-) C5
R6 R5 C6
CH2 AMP IN (+)
Figure 2: Recommended External Components
R1 R2 R3 R4 R5 R6 R7 R8 Note 1 Note 1 Note 1 Note 1
68k 68k 750k 750k 68k 68k 750k 750k
1% 1% 1% 1% 1% 1% 1% 1%
C1 C2 C3 C4 C5 C6 X1 Note 2, 3
1.0F 1.0F 270pF 270pF 270pF 270pF 3.579545MHz
20% 20% 5% 5% 5% 5%
Table 2: Recommended External Components Note: 1. Fixed Sensitivity Setting: when calculating/selecting gain components, R3, R4, R7 and R8 should always be greater than or equal to 100k. 2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. 3. The on-chip crystal circuitry includes a feedback resistor (nominally 2M) between pins 1 & 2 and load capacitors on pins 1 & 2 (nominally 10pF each, excluding package and board parasitics).
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Dual SPM Detector
Page 7 of 16
MX641 Preliminary Information
4. General Description
4.1 Xtal/Clock Distribution
The MX641 requires a 3.579545MHz Xtal or clock pulse input. With the exception of the Xtal, all oscillator components are incorporated on chip. If a Xtal input is employed the Clock Out pin should be directly linked to the Clock In pin. To reduce component and layout complexity, the clock requirements of up to 3 additional MX641 microcircuits may be supplied from a Xtal-driven MX641 acting as the system master clock. With reference to Figure 3, the clock should be distributed as illustrated and the Xtal/Clock pins of the driven microcircuits should be connected directly to VDD. Note (see section 6.1.3) that the maximum load on the master Clock Out pin should not be exceeded.
CLOCK OUT CLOCK IN CLOCK IN CLOCK IN CLOCK IN
Controller
XTAL/CLOCK X1 XTAL
MX641 (used as Master Oscillator)
Ch 1 Ch 2
VDD
MX641
MX641
MX641
XTAL/CLOCK
XTAL/CLOCK
XTAL/CLOCK
Ch 1
Ch 1
Ch 2
Ch 2
OUTPUT ENABLE
Ch 1 OUTPUT
Ch 2 OUTPUT
I/O Ports Ch 2 Ch 1 3 to'N' LINE DECODER
"OUTPUT ENABLE" ADDRESSING
Figure 3: Xtal/Clock Distribution and Output Multiplexing 4.2 Channel Outputs
Channel 1 and Channel 2 outputs operate together under the control of the Output Enable and Output Select inputs. Table 3 describes the operations. The digital output is pin-selectable to one of three modes: (1) Tone Follower mode: a logic level for the period of a correct decode. (2) Packet mode: respond/de-respond after a cumulative period of tone or notone in a fixed (intrinsic hardwired period that is not user controlled) period. (3) High-impedance output: for device multiplexing. System Select X X 0 1 0 1 X X = don't care Note: Device sensitivity and system frequency must be serially loaded
Table 3: Operating Mode Configuration
Preset Level 0 0 1 1 1 1 X
Output Select 0 1 0 0 1 1 X
Output Enable Mode 0 0 0 0 0 0 1
Operating Mode Sensitivity Frequency
Packet Mode Output; Tone Follower Output; Packet Mode Output; Packet Mode Output; Tone Follower Output; Tone Follower Output;
Serial Data Control (see note) Serial Data Control (see note) Fixed Sensitivity Fixed Sensitivity Fixed Sensitivity Fixed Sensitivity 16kHz 12kHz 16kHz 12kHz
Tristate Output (High Z)
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Dual SPM Detector
SIGNAL INPUT TONE
Page 8 of 16
NOTONE
MX641 Preliminary Information
CH1 and CH 2 OUTPUTS
TONE FOLLOWER OUTPUT
PACKET MODE OUTPUT
RESPONSE DELAY
SIGNAL INPUT ......
TONE FOLLOWER OUTPUT ...... DERESPONSE DELAY PACKET MODE OUTPUT ......
Figure 4: Tone Follower and Packet Mode Outputs 4.3 Sensitivity Setting
To enable the MX641 to operate correctly to most national 12kHz and 16kHz SPM specifications, the input sensitivity can be accurately adjusted and set. There are two different pin-selectable modes of sensitivity setting available to the MX641: Controlled Sensitivity Mode and Fixed Sensitivity Mode The Controlled Sensitivity mode allows the sensitivity setting from a Controller via a 6-bit serial data input. This same serial input also sets operation (bit 0) to either 12kHz or 16kHz systems. Both channels are set identically. The Fixed Sensitivity mode allows the sensitivity of each channel to be set to a fixed "gain" by external components at the input amplifiers. Operation to either 12kHz or 16kHz is by the System Select input.
4.3.1 Controlled Sensitivity Setting
With the external gain (sensitivity) components used as shown in Figure 2, the gain of the input stages is 19.8dB (12kHz) or 20.5dB (16kHz). For controlled sensitivity setting the gain of each bandpass filter, and therefore the device sensitivity, is adjusted by the applied serial bits D1 to D5. In the Controlled Sensitivity mode the system frequency is selected by bit D0 (`1' = 12kHz; `0' = 16kHz). Data is loaded Bit 5 (D5) first. Table 4 details the serial data inputs for the required sensitivity. Minimum, Nominal and Maximum Sensitivity figures are provided to make complete allowance for internal circuit offsets and component tolerances. 0dB(ref.) = 775mVRMS at VDD = 5.0 volts; varies directly with VDD.
Note: Device sensitivity is directly proportional to VDD
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Dual SPM Detector
Page 9 of 16
MX641 Preliminary Information
4.3.1.1
Controlled Sensitivity Setting Information
The sensitivity figures in Table 4 are based on the following: 1. The recommended amplifier components (see Figure 2) are used, providing an amplifier gain at 16kHz of 19.8dB 0.3dB or at 12kHz of 19.1dB 0.3dB. 2. A comparator sensitivity of 1.6dB(ref.) 1dB (the variation is due to filter gain error, filter output offset, comparator input offset or a combination of all 3). 3. The applied VDD is 5.0 volts; 0dB (ref.) = 775mVRMS.
12kHz System Bit D0 = `1' Serial Data Bits D5 - D1 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Bandpass Filter Gain (dB) 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 Minimum Sensitivity dB(ref.) -16.2 -17.2 -18.2 -19.2 -20.2 -21.2 -22.2 -23.2 -24.2 -25.2 -26.2 -27.2 -28.2 -29.2 -30.2 -31.2 -32.2 -33.2 -34.2 -35.2 -36.2 -37.2 -38.2 -39.2 -40.2 -41.2 -42.2 -43.2 Nominal Sensitivit y dB(ref.) -17.5 -18.5 -19.5 -20.5 -21.5 -22.5 -23.5 -24.5 -25.5 -26.5 -27.5 -28.5 -29.5 -30.5 -31.5 -32.5 -33.5 -34.5 -35.5 -36.5 -37.5 -38.5 -39.5 -40.5 -41.5 -42.5 -43.5 -44.5 Maximum Sensitivity dB(ref.) -18.8 -19.8 -20.8 -21.8 -22.8 -23.8 -24.8 -25.8 -26.8 -27.8 -28.8 -29.8 -30.8 -31.8 -32.8 -33.8 -34.8 -35.8 -36.8 -37.8 -38.8 -39.8 -40.8 -41.8 -42.8 -43.8 -44.8 -45.8 Minimum Sensitivity dB(ref.) -16.9 -17.9 -18.9 -19.9 -20.9 -21.9 -22.9 -23.9 -24.9 -25.9 -26.9 -27.9 -28.9 -29.9 -30.9 -31.9 -32.9 -33.9 -34.9 -35.9 -36.9 -37.9 -38.9 -39.9 -40.9 -41.9 -42.9 -43.9 16kHz System Bit D0 = `0' Nominal Sensitivit y dB(ref.) -18.2 -19.2 -20.2 -21.2 -22.2 -23.2 -24.2 -25.2 -26.2 -27.2 -28.2 -29.2 -30.2 -31.2 -32.2 -33.2 -34.2 -35.2 -36.2 -37.2 -38.2 -39.2 -40.2 -41.2 -42.2 -43.2 -44.2 -45.2 Maximum Sensitivity dB(ref.) -19.5 -20.5 -21.5 -22.5 -23.5 -24.5 -25.5 -26.5 -27.5 -28.5 -29.5 -30.5 -31.5 -32.5 -33.5 -34.5 -35.5 -36.5 -37.5 -38.5 -39.5 -40.5 -41.5 -42.5 -43.5 -44.5 -45.5 -46.5
These states should never be used. If sensitivities of this order are required (e.g. the Swedish Rural SPM specification), it is recommended that the Controlled Sensitivity setting be set to 20dB (10100) and external components selected to set the Input Amp gain to a higher figure. This action will prevent falsing by sub-harmonic frequencies.
Table 4: Controlled Sensitivity Setting Information
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Dual SPM Detector
Page 10 of 16
MX641 Preliminary Information
4.3.1.2
German FTZ Specification (16kHz)
The FTZ system has a Must Decode level of -21dB (ref.) and a Must-Not Decode level of -27dB (ref.). Reference to Table 4 shows that Bandpass Filter Gain settings of 5dB, 6dB or 7dB will enable an MX641 channel to meet this level specification. Figure 5 illustrates the range of these various settings. To meet the German FTZ specification, the input data (D5 to D0) must be: 00101 or or 00110 00111 0 0 0 5.0dB 6.0dB 7.0dB
Note: 1. By selecting the middle setting, the greatest noise immunity is achieved.
MUST DECODE -21dB(ref.)
-21.9
WILL DECODE
-23.2 5.0dB
-22.9 -23.9
-24.2 6.0dB -24.5 -25.5
WILL-NOT DECODE
-25.2 7.0dB
-26.5
MUST-NOT DECODE -27dB(ref.)
Figure 5: German Specification - Possible Settings 4.3.1.3 French Specification (12kHz)
This system has a Must Decode level of -17.36dB (ref.) and a Must-Not Decode level of -23.8dB (ref.). Reference to Table 4 shows that Bandpass Filter Gain settings of 2dB, 3dB or 4dB will enable an MX641 channel to meet this level specification. Figure 6 illustrates the range of these various settings. To meet the French SPM specification, the input data (D5 to D0) must be: 00010
or or
1 1 1
2.0dB 3.0dB 4.0dB
00011 00100
Note: 1. By selecting the middle setting, the greatest noise immunity is achieved.
MUST DECODE -17.36dB(ref.)
-18.2
WILL DECODE
-19.2 -19.5 2.0dB -20.2 -20.8 -20.5 3.0dB -21.8
WILL-NOT DECODE
-21.5 4.0dB -22.8
MUST-NOT DECODE
-23.8dB(ref.)
Figure 6: French Specifications - Possible Settings
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Dual SPM Detector
Page 11 of 16
MX641 Preliminary Information
4.3.2
Fixed Sensitivity Setting
In this mode the sensitivity of each channel is set by the correct selection of the components around the Channel Input Amplifier. Note that the device sensitivity is directly proportional to the applied power supply (VDD) and that the gain bandwidth product of the input opamp can attenuate the SPM signal gain at some input gain configurations.
4.3.2.1 Input Gain Calculation
The input amplifier, with external circuitry, is used to set the sensitivity of the MX641 to conform to the user's national level specification with regard to `Must' and `Must-Not' decode signal levels. With reference to the graph in Figure 7, the following steps will assist in the determination of the required gain/attenuation. Step 1 Step 2 Draw two horizontal lines from the Y-axis (Signal Level) in Figure 7. The upper line represents the required `Must' decode level. The lower line represents the required `Must-Not' decode level Mark the intersection of the upper horizontal line and the upper sloping line; drop a vertical line from this point to the X-axis (Amplifier Gain (dB)). The point where the vertical line meets the X-axis indicates the minimum Input Amp gain required for reliable decoding of valid signals Mark the intersection of the lower horizontal line and the lower sloping line; drop a vertical line from this point to the X-axis. The point where the vertical line meets the X-axis will indicate the maximum allowable Input Amp gain. Input signals at or below the `Must-Not' decode level will not be detected as long as the amplifier gain is no higher than this level.
-10
Step 3
-15
SIGNAL LEVEL (dB): 0dB ref = 775mVRMS
-20
MUST DECODE LEVEL
-25
MUST-NOT DECODE LEVEL
-30
-35
-40
-45
MINIMUM AMPLIFIER GAIN MAXIMUM AMPLIFIER GAIN
-50 -20
-15
-10
5 0 10 AMPLIFIER GAIN (dB) VDD = 5.0 (0.1) VOLTS; TEMP = -40C to 85C
-5
15
20
25
Figure 7: Input Gain Calculation Graph for use in the Fixed Sensitivity Mode 4.3.2.2 Input Gain Components
Refer to the gain components shown in Figure 2. The user should calculate and select external components (R1/R3/C3, R2/R4/C4 and R5/R7/C5, R6/R8/C6) to provide amplifier gains within the limits obtained in Steps 2 and 3. Component tolerances should not move the gain-figure outside these limits. The graph in Figure 7 is for the calculation of input gain components for an MX641 using a VDD of 5.0 (0.1) volts. It is recommended that the designed gain is near the center of the calculated range.
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Dual SPM Detector
Page 12 of 16
MX641 Preliminary Information
5. Applications
5.1.1 Input Configurations
Differential Input Common Mode Input
INPUT AMP Tip (a) Ring (b)
INPUT AMP
+
+
MX641
VBIAS
MX641
VBIAS
Figure 8: Input Configurations 5.1.2 Protection Against High Voltages
Telephone systems may have high d.c. and a.c. voltages present on the line. If the MX641 is part of a host equipment that has its own signal input protection circuitry, there will be no need for further protection as long as the voltage on any pin is limited to within VDD +0.3V and VSS -0.3V. If the host system does not have input protection, or there are signals present outside the device's specified limits, the MX641 will require protection diodes at its signal inputs (+ and -). The breakdown voltage of capacitors and the peak inverse voltage of the diodes must be sufficient to withstand the sum of the d.c. voltages plus all expected signal peaks.
5.1.3 Aliasing
Due to the sampling nature of switched-capacitor filters used in the MX641, high frequency noise or unwanted signals can alias into the passband, disrupting detection. External components must be chosen carefully to avoid alias effects. Possible Alias Frequencies: 12kHz Mode = 52kHz 16kHz Mode = 69kHz If other filtering in the system has not attenuated these alias frequencies, capacitors should be employed across resistors R3, R4, R7 and R8 to provide anti-alias filtering. The low-pass cutoff frequency should be chosen to be approximately 20kHz to 25kHz for a 12kHz system, or 25kHz to 30kHz for a 16kHz system. i.e. C =
1 2 x x f x R3
When anti-alias capacitors are used, an allowance must be made for reduced gain at the SPM frequency (12kHz or 16kHz).
a2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480115.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Dual SPM Detector
Page 13 of 16
MX641 Preliminary Information
6. Performance Specification
6.1 6.1.1 Electrical Specifications Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage.
Parameter Min. Typ. Max. Unit
Supply Voltage (VDD-VSS) Voltage on any pin to VSS Current VDD VSS Any other pin
DW / P Packages
-0.3 -0.3 -30 -30 -20
7.0 (VDD + 0.3) 30 30 20 800 10
V V mA mA mA mW mW/C above TAMB 25C C C
Total allowable device dissipation at TAMB 25C Derating above TAMB 25C Operating Temperature Storage Temperature
6.1.2 Operating Limits
-40 -40
85 85
Correct Operation of the device outside these limits is not implied.
Parameter Min. Typ. Max. Unit
Supply Voltage (VDD) Operating Temperature Xtal/Clock Frequency
6.1.3 Operating Characteristics
4.5 -40 3.558918
5.0
5.5 85 3.589368
V MHz
All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V @ TAMB = 25C Audio Level 0dB (ref.) = 775mVRMS, Noise Bandwidth = 50kHz Xtal/Clock Frequency = 3.579545MHz, System Setting = 12kHz or 16kHz
Notes Min. Typ. Max. Units
Supply Current
Input/Output Parameters
2.0 17 (High) (Low) 13 14 -5.0 -15.0 3.5
5.0 15.0
mA pF V
Clock Out Load
Logic Inputs
Input Logic `1' Input Logic `0' Input Leakage Current (VIN = 0 to VDD) Input Current (VIN = 0)
1.5 5.0
V A A
a2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480115.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Dual SPM Detector
Page 14 of 16
MX641 Preliminary Information
Notes Channel Outputs
Min.
Typ.
Max.
Units
Output Logic `1' Output Logic `0' Output Leakage Current
Input Amplifier
IOH = 120mA (Enabled) IOL = 360mA (Enabled) High-Z Output
1 1 2
4.6 0.4 -5.0 60.0 100 1.0 5.0
V V A dB Hz M 12.18 11.52 kHz kHz kHz 16.24 15.36 kHz kHz 1.6 -26.4 20.0 -40.0 -27.0 0.6 -27.4 dB(ref.) dB(ref.) dB dB dB
D. C. Gain Bandwidth (-3dB) Input Impedance
Overall Performance
12kHz Detect Bandwidth 12kHz Not-detect Frequencies 12kHz Not-detect Frequencies 16kHz Detect Bandwidth 16kHz Upper Decode Band Edge 16kHz Lower Decode Band Edge Level Sensitivity Controlled Sensitivity Mode Preset Sensitivity Mode
Signal Quality Requirements
3 (Below 12kHz) (Above 12kHz) (Below 16kHz) (Above 16kHz) 3 3 3 3 3 3,4,12,15 3,4,5,16 (Amp Input) (Amp Input) (Amp Output) (Ch1 and Ch2) Figure 4 6 3, 4, 7 4,8,9,10 4,8,9,11 4,8,10,11
11.82 12.48 15.76 16.64 2.6 -25.4 22.0 -36.0 -1.0
Signal-to-Noise Signal-to-Voice Signal-to-Voice Channel Outputs Mode Change Time Tone Follower Mode (Table 3) Response and De-Response Time Packet Mode (Table 3) Response and De-Response Time
Note: 1. 2. 3. 4. 5. 6.
500 10.0
ns ms
3, 4, 7
40.0
48.0
ms
7. 8. 9. 10.
Tone Follower or Packet mode enabled; see Table 3 Tristate selected; see Table 3. With adherence to Signal-to-Voice and Signal-to Noise specifications. 12kHz and/or 16kHz system. With Input Amp gain setting = 0dB. Time taken to change between any two of the operational modes: Tone Follower, Packet or Tristate, and with a maximum capacitive load of 30pF on an output. The time delay, after a valid serial data load (or after device powerup), before the condition of the outputs can be guaranteed correct. Immunity to false responses and/or de-responses. Common Mode SPM and balanced voice input signal. With SPM and voice signal amplitudes balanced; to avoid false de-responses due to saturation, the peak-to-peak voice + noise level at the output of the Input Amp should be no greater than the dynamic
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 Doc. # 20480115.004
a2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Dual SPM Detector
Page 15 of 16
MX641 Preliminary Information
11. 12.
13. 14. 15. 16.
17.
6.2
range of the device. For this reason, the signal-to-voice figure at the AMP Output will vary with the sensitivity setting. The lowest signal-to-voice figure occurs at the highest sensitivity setting. (Table 4 27dB) Maximum voice frequencies = 3.4kHz. With the Input Amplifier gain at 0dB and the Bandpass Filter gain set at 0dB (Table 4); subtract 1.0dB from this specification for each extra single dB of Bandpass Filter gain programmed. Alternatively, with the input components as recommended in Figure 2, the sensitivity is as defined in Table 4. Logic inputs with no internal pull-up; Chip Select, Serial Data, Serial Clock, Output Enable, Output Select and Clock In pins. Logic inputs with an internal pull-up; Preset Level and System Select pins. Preset Level = `0', System Select = don't care; Chip Select, Serial Clock and Serial Data inputs active; see Table 3. Preset Level = `1', System Select = input active; Chip Select, Serial Clock and Serial Data inputs inactive; see Table 3 Maximum Clock Output Fan out = 4 (including master)
Timing Parameter Min. Typ. Max. Unit
tPWH tPWL tCYC tCSE tDH tDS
Serial Clock `High` Pulse Width Serial Clock `Low' Pulse Width Serial Clock Period Chip Select `Low' to Clock `High' Edge Data Hold Time Data Setup Time
250 250 600 450 50.0 250
ns ns ns ns ns ns
CHIP SELECT
t CSE t CYC t CSH
SERIAL CLOCK
tDS
SERIAL DATA
tDH
Don't Care Data
tPWL
tPWH BIT D4 D3 BIT D0
BIT D5
Figure 9: Data Load Timing for the Controlled Sensitivity Mode
a2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480115.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Dual SPM Detector
Page 16 of 16
MX641 Preliminary Information
6.3
Packages
Package Tolerances
A Z B E W L T X Y CK H J P
DIM. A B C E H J K L P T W X Y Z MIN.
0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91)
TYP.
MAX.
0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17)
Alternative Pin Location Marking
PIN 1
0.050 (1.27) 0.016 (0.41) 0.050 (1.27) 0.009 (0.23) 45 0 5 5 10 7 0.0125 (0.32)
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 10: 24-pin SOIC Mechanical Outline: order as part no. MX641DW
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP. MAX.
1.270 (32.26) 1.200 (30.48) 0.555 (14.04) 0.500 (12.70) 0.151 (3.84) 0.220 (5.59) 0.600 (15.24) 0.670 (17.02) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 0.121 (3.07) 0.160 (4.05) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7 NOTE : All dimensions in inches (mm.) Angles are in degrees
B
E1
Y
E
PIN1
T
K H L
C
J
J1
P
Figure 11: 24-pin PDIP Mechanical Outline: order as part no. MX641P
a2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480115.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking On CML Microcircuits (USA) products, the `MX-COM' textual logo is being replaced by a `CML' textual logo.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/2 May 2002

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